Make minor modifications

README.md

@@ -4,6 +4,12 @@ A hardware library for customized processor or accelerator design.
 
 * [sbt](https://www.scala-sbt.org/) (required): Scala Build Tool.
 
+### Useful Links
+
+* [chisel3 wiki](https://github.com/freechipsproject/chisel3/wiki)
+* [chisel3](https://www.chisel-lang.org/api/latest/chisel3/) documentation
+* [scala](https://www.scala-lang.org/api/current/) documentation
+
 ### License
 
 * Open-Intelligence Open Source License V1.1 [[Link]](LICENSE)

src/test/scala/varec/apps/VecAddTester.scala

@@ -4,11 +4,11 @@ import chisel3._
 import chisel3.util._
 import chisel3.iotesters.{ChiselFlatSpec, PeekPokeTester}
 import varec.axi4.{AxiMasterIO}
-import varec.util.{DeqBus, EnqBus, MemIO, MemWriteIO, DramSimulator}
+import varec.util.{DeqBus, EnqBus, MemIO, DramSimulator}
 import varec.math.MathForPowerOfTwo._
 import varec.util.Constants._
 
-class VecAdd extends Module {
+class VecAddCore extends Module {
   val addr_width = 16
   val data_width = 32
 
@@ -74,16 +74,7 @@ class VecAdd extends Module {
 }
 
 class VecAddShell extends Module {
-  val core = {
-    val c = Module(new VecAdd)
-    c.io.acc.sInit()
-    c.io.opr.sInit()
-    c.io.a_ptr := 0.U
-    c.io.b_ptr := 0.U
-    c.io.c_ptr := 0.U
-    c.io.start := false.B
-    c
-  }
+  val core = Module(new VecAddCore)
 
   val io = IO(new Bundle {
     val ram = Flipped(new MemIO(math.pow(2, core.addr_width).toInt, core.data_width))
@@ -99,6 +90,8 @@ class VecAddShell extends Module {
     Seq.fill(2)(new AxiMasterIO(core.addr_width, core.data_width))))
   val acc_bus = dram_sim.io.buses(0)
   val opr_bus = dram_sim.io.buses(1)
+  acc_bus.mInit()
+  opr_bus.mInit()
 
   io.ram <> dram_sim.io.ram
   core.io.acc <> acc_bus
@@ -113,19 +106,20 @@ class VecAddShell extends Module {
 }
 
 class VecAddTester(s: VecAddShell) extends PeekPokeTester(s) {
-  val len = 16
-  val a = (0 until len)
-  val b = (0 until len).map(2 * _ + 1)
-  val c_sw = a.zip(b).map({ case (x, y) => x + y })
+  val len = 16 // vector length
+  val a = (0 until len) // some vector a
+  val b = (0 until len).map(2 * _ + 1) // some vector b
+  val c_sw = a.zip(b).map({ case (x, y) => x + y }) // vector c = a + b (software reference)
 
-  val data_size = 4
+  val data_size = 4 // bytes of 32-bit integers
   require(data_size == s.core.data_width / BYTE_WIDTH)
   require(data_size == s.io.ram.mem_width / BYTE_WIDTH)
 
-  val a_idx = 0x10
-  val b_idx = a_idx + len
-  val c_idx = b_idx + len
+  val a_idx = 0x10 // a magic number
+  val b_idx = a_idx + len // vector b placed right after vector a
+  val c_idx = b_idx + len // vector c placed right after vector b
 
+  // write vector a and b to dram simulator
   poke(s.io.ram.en, 1)
   poke(s.io.ram.we, 1)
   for (i <- 0 until len) {
@@ -139,18 +133,19 @@ class VecAddTester(s: VecAddShell) extends PeekPokeTester(s) {
   poke(s.io.ram.we, 0)
   poke(s.io.ram.en, 0)
 
-  poke(s.io.a_ptr, a_idx * data_size)
-  poke(s.io.b_ptr, b_idx * data_size)
-  poke(s.io.c_ptr, c_idx * data_size)
-  poke(s.io.start, 1)
+  // set parameters and start hardware simulation
+  poke(s.io.a_ptr, a_idx * data_size) // byte address
+  poke(s.io.b_ptr, b_idx * data_size) // byte address
+  poke(s.io.c_ptr, c_idx * data_size) // byte address
   poke(s.io.length, len)
+  poke(s.io.start, 1)
   step(1)
   poke(s.io.start, 0)
-
   while (peek(s.io.done) == 0) {
     step(1)
   }
 
+  // read vector c from dram simulator and verify
   var matched = true
   poke(s.io.ram.en, 1)
   for (i <- 0 until len) {