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Add XclAxiStreamIO

master^2
Guojie Luo 2 years ago
parent
commit
c033c6481f
1 changed files with 28 additions and 0 deletions
  1. +28
    -0
      src/main/scala/varec/shell/XclAxiIO.scala

+ 28
- 0
src/main/scala/varec/shell/XclAxiIO.scala View File

@@ -4,6 +4,34 @@ import chisel3._
import chisel3.util._
import varec.axi4.{Axi4Config, AxiLiteSlaveIO, AxiMasterIO}

object XclAxiEnqIO {
def apply(data_width: Int) = Flipped(new XclAxiStreamIO(data_width))
}

object XclAxiDeqIO {
def apply(data_width: Int) = new XclAxiStreamIO(data_width)
}

class XclAxiStreamIO(data_width: Int) extends Bundle {
val TREADY = Input(Bool())
val TVALID = Output(Bool())
val TDATA = Output(UInt(data_width.W))

def order(stream: DecoupledIO[UInt]) {
stream.ready := TREADY
TVALID := stream.valid
TDATA := stream.bits
}

def serve(stream: DecoupledIO[UInt]) {
TREADY := stream.ready
stream.valid := TVALID
stream.bits := TDATA
}

override def cloneType: this.type = new XclAxiStreamIO(data_width).asInstanceOf[this.type]
}

class XclAxiLiteSlaveIO(addr_width: Int, data_width: Int) extends Bundle {
val ARREADY = Output(Bool())
val ARVALID = Input(Bool())


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