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- package varec.core
-
- import chisel3._
- import chisel3.util._
- import chisel3.iotesters.{ChiselFlatSpec, PeekPokeTester}
- import varec.axi4.{AxiMasterIO}
- import varec.util.{MemIO, DramSimulator}
- import varec.arch.{InsnConfig}
-
- class DispatchWrapper() extends Module {
- val insn_width = 128
- val addr_width = 16
-
- val io = IO(new Bundle {
- val insn_base = Input(UInt(addr_width.W))
- val insn_count = Input(UInt(addr_width.W))
- val load_stream = Flipped(DeqIO(UInt(insn_width.W)))
- val exec_stream = Flipped(DeqIO(UInt(insn_width.W)))
- val store_stream = Flipped(DeqIO(UInt(insn_width.W)))
- val ram = Flipped(new MemIO(math.pow(2, addr_width).toInt, insn_width))
- val start = Input(Bool())
- val idle = Output(Bool())
- })
-
- val dispatch = Module(new Dispatch(new AxiMasterIO(addr_width, insn_width), InsnConfig.baseInsn))
- val sim = Module(new DramSimulator(new AxiMasterIO(addr_width, insn_width)))
-
- sim.io.bus.write_addr.mInit()
- sim.io.bus.write_data.mInit()
- sim.io.bus.write_resp.mInit()
-
- dispatch.io.insn_bus <> sim.io.bus
- dispatch.io.insn_base <> io.insn_base
- dispatch.io.insn_count <> io.insn_count
- dispatch.io.load_stream <> io.load_stream
- dispatch.io.exec_stream <> io.exec_stream
- dispatch.io.store_stream <> io.store_stream
- dispatch.io.en <> true.B
- dispatch.io.start <> io.start
- dispatch.io.idle <> io.idle
-
- sim.io.ram <> io.ram
- }
-
- class DispatchUnitTester(c: DispatchWrapper) extends PeekPokeTester(c) {
- val base = 1024
- val index = ByteToWord(base, c.insn_width / 8)
- val insn = Array(
- BigInt("0180 8000 0000 0000 0001 0040 0040 0000".split(" ").reverse.mkString(""), 16),
- BigInt("8180 0000 0001 0000 0001 0040 0040 0000".split(" ").reverse.mkString(""), 16),
- BigInt("0000 0000 0020 0000 0001 0001 0001 0000".split(" ").reverse.mkString(""), 16),
- BigInt("0044 0020 0008 0080 0400 8000 0800 0000".split(" ").reverse.mkString(""), 16),
- BigInt("0029 0000 0006 0000 0001 0040 0040 0000".split(" ").reverse.mkString(""), 16),
- BigInt("0100 0000 0000 0000 0000 0000 0000 0000".split(" ").reverse.mkString(""), 16),
- BigInt("0000 0000 0000 0000 0000 0000 0000 0000".split(" ").reverse.mkString(""), 16),
- BigInt("0003 0000 0000 0000 0000 0000 0000 0000".split(" ").reverse.mkString(""), 16)
- )
-
- poke(c.io.ram.en, 1) // DramSimualtor at ram mode
-
- poke(c.io.ram.we, 1)
- for (i <- 0 until insn.length) {
- poke(c.io.ram.index, index + i)
- poke(c.io.ram.din, insn(i))
- step(1)
- }
- poke(c.io.ram.we, 0)
-
- poke(c.io.ram.en, 0) // DramSimulator at bus mode
-
- poke(c.io.insn_base, base)
- poke(c.io.insn_count, insn.length)
- poke(c.io.start, 1)
- step(1)
- poke(c.io.start, 0)
-
- deq(c.io.exec_stream, insn(0))
- deq(c.io.exec_stream, insn(1))
- deq(c.io.exec_stream, insn(2))
- deq(c.io.exec_stream, insn(3))
- deq(c.io.store_stream, insn(4))
- deq(c.io.load_stream, insn(5))
- deq(c.io.exec_stream, insn(6))
- deq(c.io.exec_stream, insn(7))
-
- step(1)
- expect(c.io.idle, 1)
-
- def deq(stream: DecoupledIO[UInt], bits: BigInt) {
- poke(stream.ready, 1)
- while (peek(stream.valid) == 0) {
- step(1)
- }
- expect(stream.bits, bits)
- step(1)
- }
- }
-
- object DispatchTester extends App {
- iotesters.Driver.execute(args, () => new DispatchWrapper()) { c => new DispatchUnitTester(c) }
- }
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