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- package varec.core
-
- import chisel3._
- import chisel3.util._
- import chisel3.iotesters.{ChiselFlatSpec, PeekPokeTester}
- import varec.axi4.{AxiMasterIO, AxiMasterReadIO}
- import varec.util.{MemIO, MemReadIO, MemWriteIO, SimpleDualPortMem, DramSimulator}
- import varec.arch.{InsnConfig}
- import varec.arch.VarecConfig._
-
- class StoreWrapper() extends Module {
- val addr_width = 16
- val insn_width = 128
- val uops_width = 32
- val bias_width = 512
-
- val io = IO(new Bundle {
- val insn_stream = Flipped(EnqIO(UInt(INSN_WIDTH.W)))
- val sem_wait = Flipped(EnqIO(Bool()))
- val sem_post = Flipped(DeqIO(Bool()))
-
- val out_base = Input(UInt(addr_width.W))
- val out_mem = Flipped(new MemWriteIO(ACC_BUFF_DEPTH * BATCH, OUT_WIDTH * BLOCK_OUT))
- val out_ram = Flipped(new MemReadIO(math.pow(2, addr_width).toInt, bias_width))
-
- val idle = Output(Bool())
- })
-
- val out_mem = Module(new SimpleDualPortMem(ACC_BUFF_DEPTH * BATCH, OUT_WIDTH * BLOCK_OUT))
- val out_ram = Module(new DramSimulator(new AxiMasterIO(addr_width, bias_width)))
- val store = Module(new Store(out_ram.io.bus, InsnConfig.dataInsn))
-
- out_ram.io.bus.mInit()
- out_ram.io.ram.disable()
-
- store.io.data_bus <> out_ram.io.bus
- store.io.out_base <> io.out_base
- store.io.insn_stream <> io.insn_stream
- store.io.sem_wait <> io.sem_wait
- store.io.sem_post <> io.sem_post
- store.io.out_mem <> out_mem.io.b
-
- store.io.en <> true.B
- store.io.idle <> io.idle
-
- out_mem.io.a <> io.out_mem
- out_ram.io.ram <> io.out_ram
- }
-
- class StoreUnitTester(c: StoreWrapper) extends PeekPokeTester(c) {
- val insn = Array(
- BigInt("0029 0000 0006 0000 0001 0040 0040 0000".split(" ").reverse.mkString(""), 16), // store
- )
- val mem_base = 0x0000
- val ram_base = 0x3000
- assert(ram_base % (c.bias_width / 8) == 0)
-
- val size = 64
- //val size = 8
-
- poke(c.io.insn_stream.valid, 0)
-
- // init out_mem
- poke(c.io.out_mem.en, 1)
- poke(c.io.out_mem.we, 1)
- for (i <- 0 until size) {
- poke(c.io.out_mem.index, mem_base + i)
- poke(c.io.out_mem.din, BigInt((0 to 15).map(j => "%02x".format((16 * i + j) % 128 + 2)).reverse.mkString(""), 16))
- step(1)
- }
- poke(c.io.out_mem.en, 0)
- poke(c.io.out_mem.we, 0)
-
- // feed insn
- for (i <- 0 until insn.length) {
- poke(c.io.insn_stream.bits, insn(i))
- poke(c.io.insn_stream.valid, 1)
- while (peek(c.io.insn_stream.ready) == 0) {
- println(s"insn step ${t}")
- step(1)
- }
- step(1)
- }
- poke(c.io.insn_stream.valid, 0)
-
- poke(c.io.sem_wait.bits, 1)
- poke(c.io.sem_wait.valid, 1)
- while (peek(c.io.sem_wait.ready) == 0) {
- println(s"sem_wait step ${t}")
- step(1)
- }
- step(1)
- poke(c.io.sem_wait.valid, 0)
-
- poke(c.io.sem_post.ready, 1)
- while (peek(c.io.sem_post.valid) == 0) {
- //println(s"sem_post step ${t}")
- step(1)
- }
- step(1)
- poke(c.io.sem_post.ready, 0)
-
- while (peek(c.io.idle) == 0) {
- println(s"idle step ${t}")
- step(1)
- }
- step(1)
-
- // check
- poke(c.io.out_ram.en, 1)
- for (i <- 0 until size / 4) {
- val index = ram_base / (c.bias_width / 8) + i
- poke(c.io.out_ram.index, index)
- step(1)
- val data = peek(c.io.out_ram.dout)
- val edata = BigInt((0 until 16 * 4).map(j => "%02x".format((16 * i * 4 + j) % 128 + 2)).reverse.mkString(""), 16)
- //println(s"${data.toString(16)} ${edata.toString(16)}")
- expect(c.io.out_ram.dout, edata)
- }
- poke(c.io.out_ram.en, 0)
- }
-
- object StoreTester extends App {
- iotesters.Driver.execute(args, () => new StoreWrapper()) { c => new StoreUnitTester(c) }
- }
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