|
- //
- // Generated by NVIDIA NVVM Compiler
- //
- // Compiler Build ID: CL-26907403
- // Cuda compilation tools, release 10.1, V10.1.243
- // Based on LLVM 3.4svn
- //
-
- .version 6.4
- .target sm_60
- .address_size 64
-
- // .globl Fused_MaximumGrad_Mul_Add_fusion_12121628495452321337_kernel0
-
- .visible .entry Fused_MaximumGrad_Mul_Add_fusion_12121628495452321337_kernel0(
- .param .u64 Fused_MaximumGrad_Mul_Add_fusion_12121628495452321337_kernel0_param_0,
- .param .u64 Fused_MaximumGrad_Mul_Add_fusion_12121628495452321337_kernel0_param_1,
- .param .u64 Fused_MaximumGrad_Mul_Add_fusion_12121628495452321337_kernel0_param_2,
- .param .u64 Fused_MaximumGrad_Mul_Add_fusion_12121628495452321337_kernel0_param_3
- )
- {
- .reg .pred %p<5>;
- .reg .f32 %f<46>;
- .reg .b32 %r<10>;
- .reg .b64 %rd<14>;
-
-
- ld.param.u64 %rd1, [Fused_MaximumGrad_Mul_Add_fusion_12121628495452321337_kernel0_param_0];
- ld.param.u64 %rd2, [Fused_MaximumGrad_Mul_Add_fusion_12121628495452321337_kernel0_param_1];
- ld.param.u64 %rd3, [Fused_MaximumGrad_Mul_Add_fusion_12121628495452321337_kernel0_param_2];
- ld.param.u64 %rd4, [Fused_MaximumGrad_Mul_Add_fusion_12121628495452321337_kernel0_param_3];
- cvta.to.global.u64 %rd5, %rd1;
- cvta.to.global.u64 %rd6, %rd2;
- cvta.to.global.u64 %rd7, %rd3;
- mov.u32 %r1, %ctaid.x;
- shl.b32 %r2, %r1, 12;
- mov.u32 %r3, %tid.x;
- shl.b32 %r4, %r3, 2;
- add.s32 %r5, %r4, %r2;
- mul.wide.s32 %rd8, %r5, 4;
- add.s64 %rd9, %rd7, %rd8;
- ld.global.nc.v4.f32 {%f1, %f2, %f3, %f4}, [%rd9];
- add.s64 %rd10, %rd6, %rd8;
- ld.global.nc.v4.f32 {%f9, %f10, %f11, %f12}, [%rd10];
- add.s64 %rd11, %rd5, %rd8;
- ld.global.nc.v4.f32 {%f17, %f18, %f19, %f20}, [%rd11];
- setp.le.f32 %p1, %f9, %f17;
- mul.f32 %f25, %f1, 0f3E4CCCCD;
- selp.f32 %f26, %f25, 0f00000000, %p1;
- selp.u32 %r6, 1, 0, %p1;
- cvt.rn.f32.s32 %f27, %r6;
- mov.f32 %f28, 0f3F800000;
- sub.f32 %f29, %f28, %f27;
- setp.le.f32 %p2, %f10, %f18;
- mul.f32 %f30, %f2, 0f3E4CCCCD;
- selp.f32 %f31, %f30, 0f00000000, %p2;
- selp.u32 %r7, 1, 0, %p2;
- cvt.rn.f32.s32 %f32, %r7;
- sub.f32 %f33, %f28, %f32;
- setp.le.f32 %p3, %f11, %f19;
- mul.f32 %f34, %f3, 0f3E4CCCCD;
- selp.f32 %f35, %f34, 0f00000000, %p3;
- selp.u32 %r8, 1, 0, %p3;
- cvt.rn.f32.s32 %f36, %r8;
- sub.f32 %f37, %f28, %f36;
- setp.le.f32 %p4, %f12, %f20;
- mul.f32 %f38, %f4, 0f3E4CCCCD;
- selp.f32 %f39, %f38, 0f00000000, %p4;
- selp.u32 %r9, 1, 0, %p4;
- cvt.rn.f32.s32 %f40, %r9;
- sub.f32 %f41, %f28, %f40;
- cvta.to.global.u64 %rd12, %rd4;
- add.s64 %rd13, %rd12, %rd8;
- fma.rn.f32 %f42, %f4, %f41, %f39;
- fma.rn.f32 %f43, %f3, %f37, %f35;
- fma.rn.f32 %f44, %f2, %f33, %f31;
- fma.rn.f32 %f45, %f1, %f29, %f26;
- st.global.v4.f32 [%rd13], {%f45, %f44, %f43, %f42};
- ret;
- }
-
|